The present invention relates generally to the field of sensors, and more particularly to an improved pixel architecture with increased signal to noise ratio and circuitry for linearizing the output response.
Two-dimensional large-area sensor arrays have wide ranging applications in medical imaging, optical scanning, chemical or radiation detection, temperature sensing, and other arts. Such sensors comprise a grid of pixels, with each pixel composed of at least a sensor device and one or more transistors comprising a circuit for converting sensory data (such as optical images, x-ray images with or without the assistance of a scintillation layer, chemical presence, temperature, etc.) to electrical signals (typically data used for processing, storing, driving a display or an alarm, etc.) The sensor is generally a reverse biased diode, and the transistor(s) is generally a thin-film field effect transistor (TFT). Conveniently, each of the components of the pixel may be formed of hydrogenated amorphous silicon (a-Si) to take advantage of the ease of fabrication of large area arrays, low leakage current devices, and other benefits of using this amorphous material. (A component will be referred to herein as being formed of a-Si when at least one layer of the component is formed of said material. For example, as used herein, an a-Si TFT refers to a thin film transistor having an amorphous silicon channel layer.)
It should be clear from the above that the sensors of the type relevant to the present invention are designed to sense one or more of a variety of sensory data (e.g., light, radiation, chemical, thermal, etc.). An important subset of this group of sensors is comprised of sensors optimized to sense image data. While the discussions herein are broadly applicable to sensory data, the following discussion will focus on image data for clarity of explanation.
It is known that a critical parameter of an array of image sensors is the signal to noise ratio of the array. Namely, a reduction of noise as compared to signal is generally desirable. Signal amplifiers are typically employed to boost sensed signals for downstream use. It is common practice to connect an entire row of image sensors to a single amplifier. There are numerous advantages to this architecture, including minimizing the number of contacts to the array, maximizing the fill factor (defined as the fraction of the area of the array sensitive to the incident image), etc.
However, the noise in such an architecture is related to both the readout noise due to the large capacitance of the long data line, and the pixel noise which is a function of the pixel architecture itself and which is amplified together with the signal itself. For example, the thermal noise of the readout amplifier is proportional to the capacitance on the input of the amplifier.
Accordingly, it has been suggested that each pixel be provided with its own amplifier circuitry. In copending U.S. patent application Ser. No. 08/699,875, now U.S. Pat. No. 5,831,258, to Street et al. (referred to herein as "Street et al."), a pixel circuit and array incorporating such a circuit is disclosed. Typically, such a circuit consists of a photosensor with inherent capacitance for storing a charge under reversed bias conditions. The stored charge is depleted by light incidence. Determining the intensity of the incident light is accomplished by examining the remaining charge in the photosensor. The photosensor may be connected in reverse bias mode between a data line and a bias line. The photosensor is connected to a transistor or transistors such that the voltage through the transistor(s), between the bias line and the data line, is a function of the amount of light incident upon the photosensor. This structure is referred to as an amplified pixel.
In addition to increasing the signal to noise ratio, it is also a perennial goal in the image sensor art to provide increased resolution from sensor arrays. For example, a pixel having an area on the order of (150 .mu.m).sup.2, as taught by Street et al., corresponds to a resolution of approximately 170 dpi, and qualifies as a low resolution sensor by current measures.
It is generally understood that reducing pixel area is a means of increasing resolution. However, there are several penalties generally paid when pixel area is reduced. The first is that the area of the photosensor is reduced. This results in a decrease in sensitivity of the photosensor. The second is that one or more of the dimensions of the pixel transistors are reduced. In the case of an amplified pixel, this runs the risk of reducing gain below an acceptable threshold. For example, in the case of a single transistor amplifier, an a-Si TFT with a ratio of channel width (W) to channel length (L) of 4 provides a desired gain of approximately 10. A reduction in the width to length ratio (W/L), however, results in a reduction in gain. The combination of current process limitations leading to a minimum device dimension of L.gtoreq.5 .mu.m for a-Si devices, combined with the low carrier mobility of a-Si, means that a channel of 5 .mu.m.times.20 .mu.m is as small as current technology will permit while providing adequate gain. However, there is a desire to overcome this barrier and produce smaller pixels for increased resolution.
It will be appreciated that there are two parameters of a sensor circuit at odds with the desire to reduce pixel size. The first is the desire to maximize the sensitivity of the pixel. This can be accomplished by increasing the physical size of the photosensor part of the circuit, but at the cost of increasing the entire pixel size. Rather than increasing pixel size, it is common in the art to increase the area of the cell dedicated to the photosensor, referred to as the fill factor. As between two sensor pixels who differ only in photosensor area, the one with the larger photosensor area (greater fill factor) will generally provide better sensitivity. However, for a given pixel size, generally the larger the area occupied by transistor(s), the smaller the area available for the photosensor. Given the lower limit on transistor size, a tradeoff must therefore be made between resolution and sensitivity.
The second parameter at odds with the desire to reduce pixel size is the complexity of the circuit. A minimal circuit requires a photosensor and a selector switch (e.g., a transistor). However, this circuit does not address the need to do any amplification or in situ signal processing, etc. While the added circuitry is desirable from a pixel performance perspective, it undesirably consumes pixel area (and reduces yield). A tradeoff must thus be made between pixel size or fill factor and circuit complexity.